Semiconductor circuit fabrication continually seeks to reduce device configurations to increase device density and overall system speed. In reducing the size of these devices, the individual, physical layers that form these devices have also been reduced. For example, the gate oxide layer has become increasingly thinner with the reduction of typical transistor devices. The thinning of the gate oxide layer presents greater sensitivity of the devices to electrostatic discharge (ESD) which results in increased device breakdown.
Protection transistors are often included in circuits to specifically handle ESD events. In CMOS (complementary metal oxide semiconductor) fabrication, introducing a particular dopant impurity into the source/drain region of a selected number of NMOS transistors has been found to often improve the robustness of the ESD characteristics of these transistors. One such example includes implanting a lighter dose of a phosphorous implant into the source/drain of output NMOS ESD protection transistors in the CMOS circuit.
Unfortunately, the impurity implant can alter the characteristics of non-ESD transistors in the circuit, including causing an increase in the short channel and hot electron effects. However, introducing another masking step in order to "hide" these transistors from the implant increases processing complexity and manufacturing costs.
What is needed therefore is the introduction of the impurity implant to selected ESD transistors while minimizing the impact on the remaining transistors without requiring an additional masking.
The present invention addresses these needs.